HD6432345 Datasheet, PDF (170/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

6.4.4 Basic Timing
8-Bit 2-State Access Space: Figure 6.6 shows the bus timing for an 8-bit 2-state access space.
When an 8-bit access space is accessed , the upper half (D₁₅ to D₈) of the data bus is used.
The LWR pin is fixed high. Wait states cannot be inserted.
Bus cycle
T₁
T₂
ø
Address bus
CSn
AS
RD
Read
D₁₅ to D₈
Valid
D₇ to D₀
Invalid
HWR
Write
LWR
D₁₅ to D₈
High
Valid
D₇ to D₀
High impedance
Note: n = 0 to 3
Figure 6.6 Bus Timing for 8-Bit 2-State Access Space
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