HD6432345 Datasheet, PDF (153/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

6.2 Register Descriptions
6.2.1 Bus Width Control Register (ABWCR)
Bit
:
7
ABW7
Modes 1 to 3*, 5 to 7
Initial value :
1
RW
:
R/W
Mode 4
Initial value :
0
RW
:
R/W
6
ABW6
1
R/W
0
R/W
5
ABW5
1
R/W
0
R/W
4
ABW4
1
R/W
0
R/W
3
ABW3
1
R/W
0
R/W
2
ABW2
1
R/W
0
R/W
1
ABW1
1
R/W
0
R/W
0
ABW0
1
R/W
0
R/W
ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or
16-bit access.
ABWCR sets the data bus width for the external memory space. The bus width for on-chip
memory and internal I/O registers is fixed regardless of the settings in ABWCR.
In normal mode*, the settings of bits ABW7 to ABW1 have no effect on operation.
After a power-on reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 1,
2, 3*, and 5, 6, 7, and to H'00 in mode 4. It is not initialized by a manual reset or in software
standby mode.
Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the
corresponding area is to be designated for 8-bit access or 16-bit access. In normal mode*, only
part of area 0 is enabled, and the ABW0 bit selects whether external space is to be designated for
8-bit access or 16-bit access.
Note: * ZTAT, mask ROM, and ROMless versions only.
Bit n
ABWn
0
1
Description
Area n is designated for 16-bit access
Area n is designated for 8-bit access
(n = 7 to 0)
134