HD6432345 Datasheet, PDF (423/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

11.4 Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR.
11.5 Usage Notes
11.5.1 Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T₂ state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 11.8 shows this operation.
TCNT write cycle
T₁
T₂
ø
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 11.8 Contention between TCNT Write and Increment
11.5.2 Changing Value of CKS2 to CKS0
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the value of bits CKS2 to CKS0.
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