HD6432345 Datasheet, PDF (743/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Figure A.1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals
during execution of the above instruction with an 8-bit bus, using three-state access with no wait
states.
ø
Address bus
RD
HWR, LWR
High level
R:W 2nd
Fetching
3rd byte
of instruction
Fetching
4th byte
of instruction
Internal
operation
R:W EA
Fetching
1nd byte of
instruction at
jump address
Fetching
2nd byte of
instruction at
jump address
Figure A.1 Address Bus, RD, HWR, and LWR Timing
(8-Bit Bus, Three-State Access, No Wait States)
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