HD6432345 Datasheet, PDF (291/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Port G Data Register (PGDR)
Bit
:
7
6
5
4
3
2
1
0
—
—
— PG4DR PG3DR PG2DR PG1DR PG0DR
Initial value : Undefined Undefined Undefined 0
0
0
0
0
R/W
:
—
—
—
R/W
R/W
R/W
R/W
R/W
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG₄ to
PG₀).
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
Port G Register (PORTG)
Bit
:
7
6
5
4
—
—
—
PG4
Initial value : Undefined Undefined Undefined —*
R/W
:
—
—
—
R
Note: * Determined by state of pins PG4 to PG0.
3
PG3
—*
R
2
PG2
—*
R
1
PG1
—*
R
0
PG0
—*
R
PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port G pins (PG₄ to PG₀) must always be performed on PGDR.
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G
read is performed while PGDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTG contents are determined by the pin
states, as PGDDR and PGDR are initialized. PORTG retains its prior state after a manual reset,
and in software standby mode.
274