HD6432345 Datasheet, PDF (649/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Clock Timing: Table 20.4 lists the clock timing
Table 20.4 Clock Timing
Condition A: —In planning stage—
V_CC = AV_CC = 3.0 to 5.5 V, V_ref = 3.0 V to AV_CC, V_SS = AV_SS = 0 V,
ø = 2 to 10 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition B: V_CC = AV_CC = 5.0 V ± 10%, V_ref = 4.5 V to AV_CC, V_SS = AV_SS = 0 V,
ø = 2 to 20 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Item
Clock cycle time
Clock high pulse width
Clock low pulse width
Clock rise time
Clock fall time
Clock oscillator setting
time at reset (crystal)
Clock oscillator setting time
in software standby (crystal)
External clock output
stabilization delay time
Condition A
Symbol Min Max
t _cyc
t _CH
t _CL
t _Cr
t _Cf
t _OSC1
100 500
35 —
35 —
— 15
— 15
20 —
t _OSC2
8
—
t _DEXT
500 —
Condition B
Min Max Unit
50 500 ns
20 — ns
20 — ns
—5
ns
—5
ns
10 — ms
8
— ms
500 — µs
Test Conditions
Figure 20.7
Figure 20.8
Figure 19.2
Figure 20.8
640