HD6432345 Datasheet, PDF (575/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

17.7.2 Flash Memory Control Register 2 (FLMCR2)
Bit
7
6
5
4
3
FLER
—
—
—
—
Initial value 0
0
0
0
0
Read/Write R
—
—
—
—
2
1
0
—
ESU PSU
0
0
0
—
R/W R/W
FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory program/erase
protection (error protection) and performs setup for flash memory program/erase mode. FLMCR2
is initialized to H'00 by a reset, and in hardware standby mode. The ESU and PSU bits are cleared
to 0 in software standby mode, hardware protect mode, and software protect mode.
When on-chip flash memory is disabled, a read will return H'00.
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-
protect mode.
Bit 7
FLER
0
1
Description
Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Reset or hardware standby mode
An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See section 17.10.3, Error Protection
(Initial value)
Bits 6 to 2—Reserved: Read-only bits, always read as 0.
Bit 1—Erase Setup (ESU): Prepares for a transition to erase mode. Set this bit to 1 before setting
the E bit to 1 in FLMCR1. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time.
Bit 1
ESU
0
1
Description
Erase setup cleared
Erase setup
[Setting condition]
When FWE = 1, and SWE = 1
(Initial value)
563