HD6432345 Datasheet, PDF (284/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

• Modes 1, 2, 4, 5, and 6*
Pin PF₇ functions as the ø output pin when the corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
The input/output direction specified by PFDDR is ignored for pins PF₆ to PF₃, which are
automatically designated as bus control outputs (AS, RD, HWR, and LWR).
Pins PF₂ to PF₀ are designated as bus control input/output pins (WAIT, BACK, BREQ) by
means of bus controller settings. At other times, setting a PFDDR bit to 1 makes the
corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input port.
• Modes 3 and 7*
Setting a PFDDR bit to 1 makes the corresponding port F pin PF₆ to PF₀ an output port, or in
the case of pin PF₇, the ø output pin. Clearing the bit to 0 makes the pin an input port.
Port F Data Register (PFDR)
Bit
:
Initial value :
R/W
:
7
PF7DR
0
R/W
6
PF6DR
0
R/W
5
PF5DR
0
R/W
4
PF4DR
0
R/W
3
PF3DR
0
R/W
2
PF2DR
0
R/W
1
PF1DR
0
R/W
0
PF0DR
0
R/W
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF₇ to PF₀).
PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state after a manual reset, and in software standby mode.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Modes 2, 3, 6, and 7 are not available on the ROMless version.
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