HD6432345 Datasheet, PDF (37/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table 1.3 Pin Functions (cont)
Type
Interrupts
Address bus
Data bus
Bus control
Symbol
NMI
IRQ7 to
IRQ0
A₂₃ to
A₀
D₁₅ to
D₀
CS3 to
CS0
AS
RD
HWR
LWR
WAIT
Pin No.
FP-100B,
TFP-100B,
TFP-100G FP-100A I/O
Name and Function
63
65
Input Nonmaskable interrupt: Requests a
nonmaskable interrupt. When this pin
is not used, it should be fixed high.
94, 93,
13, 12,
73 to 76
96, 95,
15, 14,
75 to 78
Input
Interrupt request 7 to 0: These pins
request a maskable interrupt.
2, 1,
100, 99,
53 to 50,
48 to 41,
39 to 32
4 to 1,
55 to 52,
50 to 43,
41 to 34
Output Address bus: These pins output an
address.
30 to 19, 32 to 21, I/O
17 to 14 19 to 16
Data bus: These pins constitute a
bidirectional data bus.
94 to 97 96 to 99 Output Chip select: Signals for selecting
areas 3 to 0.
70
72
Output Address strobe: When this pin is low,
it indicates that address output on the
address bus is enabled.
71
73
Output Read: When this pin is low, it
indicates that the external address
space can be read.
72
74
Output High write: A strobe signal that writes
to external space and indicates that
the upper half (D₁₅ to D₈) of the data
bus is enabled.
73
75
Output Low write: A strobe signal that writes
to external space and indicates that
the lower half (D₇ to D₀) of the data
bus is enabled.
74
76
Input Wait: Requests insertion of a wait
state in the bus cycle when
accessing external 3-state address
space.
17