HD6432345 Datasheet, PDF (550/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

17.1.2 Register Configuration
The H8S/2345’s on-chip ROM is controlled by the mode pins and register BCRL. The register
configuration is shown in table 17.1.
Table 17.1 ROM Register
Name
Abbreviation
R/W
Mode control register
MDCR
R/W
Bus control register L
BCRL
R/W
Note: * Lower 16 bits of the address.
Initial Value
Undefined
Undefined
Address*
H'FF3B
H'FED5
17.2 Register Descriptions
17.2.1 Mode Control Register (MDCR)
Bit
:
7
6
5
4
—
—
—
—
Initial value :
1
0
0
0
R/W
:—
—
—
—
Note: * Determined by pins MD₂ to MD₀.
3
2
1
0
—
MDS2 MDS1 MDS0
0
—*
—*
—*
—
R
R
R
MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2345
Series.
Bit 7—Reserved: Read-only bit, always read as 1.
Bits 6 to 3—Reserved: Read-only bits, always read as 0.
Bits 2 to 0—Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins
MD₂ to MD₀ (the current operating mode). Bits MDS2 to MDS0 correspond to pins MD₂ to MD₀.
MDS2 to MDS0 are read-only bits, and cannot be written to. The mode pin (MD₂ to MD₀) input
levels are latched into these bits when MDCR is read. These latches are canceled by a power-on
reset, but are retained after a manual reset.
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