HD6432345 Datasheet, PDF (415/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock
sources, obtained by dividing the system clock (ø), for input to TCNT.
Bit 2 Bit 1 Bit 0 Description
CKS2 CKS1 CKS0 Clock
Overflow Period (when ø = 20 MHz)*
0
0
0
ø/2 (initial value) 25.6 µs
1
ø/64
819.2 µs
1
0
ø/128
1.6 ms
1
ø/512
6.6 ms
1
0
0
ø/2048
26.2 ms
1
ø/8192
104.9 ms
1
0
ø/32768
419.4 ms
1
ø/131072
1.68 s
Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow
occurs.
11.2.3 Reset Control/Status Register (RSTCSR)
Bit
:
7
6
5
4
3
2
1
0
WOVF RSTE RSTS
—
—
—
—
—
Initial value:
0
0
0
1
1
1
1
1
R/W
: R/(W)* R/W R/W
—
—
—
—
—
Note: * Can only be written with 0 for flag clearing.
RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal
reset signal caused by overflows.
Note: * The method for writing to RSTCSR is different from that for general registers to prevent
inadvertent overwriting. For details see section 11.2.4, Notes on Register Access.
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