HD6432345 Datasheet, PDF (192/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

7.1.2 Block Diagram
Figure 7.1 shows a block diagram of the DTC.
The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to
the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register
information and hence helping to increase processing speed.
Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Interrupt controller DTC
Internal address bus
On-chip
RAM
Interrupt
request
CPU interrupt
request
Internal data bus
Legend
MRA, MRB
: DTC mode registers A and B
CRA, CRB
: DTC transfer count registers A and B
SAR
: DTC source address register
DAR
: DTC destination address register
DTCERA to DTCERE : DTC enable registers A to E
DTVECR
: DTC vector register
Figure 7.1 Block Diagram of DTC
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