HD6432345 Datasheet, PDF (248/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Port 3 Data Direction Register (P3DDR)
Bit
:
7
6
5
4
3
2
1
0
—
— P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Initial value : Undefined Undefined 0
0
0
0
0
0
R/W
:
—
—
W
W
W
W
W
W
P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 3. Bits 7 and 6 are reserved. P3DDR cannot be read; if it is, an undefined value will be
read.
Setting a P3DDR bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P3DDR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode. As the SCI is initialized,
the pin states are determined by the P3DDR and P3DR specifications.
Port 3 Data Register (P3DR)
Bit
:
7
6
5
4
3
2
1
0
—
— P35DR P34DR P33DR P32DR P31DR P30DR
Initial value : Undefined Undefined 0
0
0
0
0
0
R/W
:
—
—
R/W
R/W
R/W
R/W
R/W
R/W
P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P3₅ to P3₀).
Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified.
P3DR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
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