HD6432345 Datasheet, PDF (486/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Restrictions on Use of DTC
• When an external clock source is used as the serial clock, the transmit clock should not be
input until at least 5 ø clock cycles after TDR is updated by the DTC. Misoperation may occur
if the transmit clock is input within 4 ø clocks after TDR is updated. (Figure 12.22)
• When RDR is read by the DTC, be sure to set the activation source to the relevant SCI
reception end interrupt (RXI).
SCK
TDRE
Serial data
t
LSB
D0
D1
D2
D3
D4
D5
D6
D7
Note: When operating on an external clock, set t >4 clocks.
Figure 12.22 Example of Clocked Synchronous Transmission by DTC
Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been
requested, it will not be possible to clear the CPU interrupt source or DTC activation source.
Interrupts should therefore be disabled before entering module stop mode.
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