HD6432345 Datasheet, PDF (101/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Modes 4 and 5
(advanced expanded modes
with on-chip ROM disabled)
H'000000
Mode 6
(advanced expanded mode
with on-chip ROM enabled)
H'000000
Mode 7
(advanced single-chip mode)
H'000000
On-chip ROM
On-chip ROM
External address
space
H'00FFFF
H'010000
H'00FFFF
H'010000
On-chip ROM/
external address
space^*1
On-chip ROM/
reserved area^*2
H'FFEC00
On-chip RAM^*3
H'FFFC00 External address
space
H'FFFE40 _{Internal I/O registers}
H'FFFF08 External address
space
H'FFFF28
H'FFFFFF
Internal I/O registers
H'01FFFF
H'020000 External address
space
H'FFEC00
On-chip RAM^*3
H'FFFC00 ^{External address}
space
H'FFFE40 _{Internal I/O registers}
H'FFFF08 External address
space
H'FFFF28
H'FFFFFF
Internal
I/O
registers
H'01FFFF
H'FFEC00
H'FFFBFF
On-chip RAM
H'FFFE40
H'FFFF07
Internal I/O registers
H'FFFF28
H'FFFFFF
Internal I/O registers
Notes: 1. When the EAE bit in BCRL is set to 1, this area is external address space.
When the EAE bit is cleared to 0, it is on-chip ROM.
2. When the EAE bit in BCRL is set to 1, this area is reserved.
When the EAE bit is cleared to 0, it is on-chip ROM.
3. External addresses can be accessed by clearing the RAME bit in SYSCR to 0.
Figure 3.1 Memory Map in Each Operating Mode in the H8S/2345 (cont)
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