HD6432345 Datasheet, PDF (199/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Bit n—DTC Activation Enable (DTCEn)
Bit n
DTCEn
0
Description
DTC activation by this interrupt is disabled
[Clearing conditions]
• When the DISEL bit is 1 and the data transfer has ended
• When the specified number of transfers have ended
(Initial value)
1
DTC activation by this interrupt is enabled
[Holding condition]
When the DISEL bit is 0 and the specified number of transfers have not ended
(n = 7 to 0)
A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence
between interrupt sources and DTCE bits is shown in table 7.4, together with the vector number
generated for each interrupt controller.
7.2.8 DTC Vector Register (DTVECR)
Bit
:
Initial value:
R/W
:
7
6
5
4
3
2
1
0
SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0
0
0
0
0
0
0
0
0
R/(W)* R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1
is read.
DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by
software, and sets a vector number for the software activation interrupt.
DTVECR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by
software.
When clearing the SWDTE bit to 0 by software, write 0 to SWDTE after reading SWDTE set to 1.
181