HD6432345 Datasheet, PDF (196/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

7.2.2 DTC Mode Register B (MRB)
Bit
:
Initial value:
R/W
:
7
CHNE
Unde-
fined
—
6
DISEL
Unde-
fined
—
5
—
Unde-
fined
—
4
—
Unde-
fined
—
3
—
Unde-
fined
—
2
—
Unde-
fined
—
1
—
Unde-
fined
—
0
—
Unde-
fined
—
MRB is an 8-bit register that controls the DTC operating mode.
Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a
number of data transfers can be performed consecutively in response to a single transfer request.
In data transfer with CHNE set to 1, determination of the end of the specified number of transfers,
clearing of the interrupt source flag, and clearing of DTCER is not performed.
Bit 7
CHNE
0
1
Description
End of DTC data transfer (activation waiting state is entered)
DTC chain transfer (new register information is read, then data is transferred)
Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are
disabled or enabled after a data transfer.
Bit 6
DISEL
0
1
Description
After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is
0 (the DTC clears the interrupt source flag of the activating interrupt to 0)
After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the
interrupt source flag of the activating interrupt to 0)
Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2345 Series, and
should always be written with 0 in a write.
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