HD6432345 Datasheet, PDF (4/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Page
Item
Revision
160
Figure 6.14 Example of Wait Insertion Amended
Timing
273
8.12.2 Register Configuration, Port G
Description amended
Data Direction Register (PGDDR)
294 to 309 9.2.3 Timer I/O Control Register (TIOR) Amended (Register name added to tables)
420
12.2.5 Serial Mode Register (SMR)
Description of bit 3 amended
429 to 431 Table 12.3 BRR Settings for Various Bit
Rates (Asynchronous Mode)
Amendments to some Error column
entries (values not entered for error of 3%
or above)
441
Figure 12.2 Data Format in Asynchronous Amended
Communication (Example with 8-Bit Data,
Parity, Two Stop Bits)
461
Figure 12.15 Sample SCI Initialization Note added
Flowchart
467
Figure 12.20 Sample Flowchart of
Note amended
Simultaneous Serial Transmit and Receive
Operations
478, 479 13.2.2 Serial Status Register (SSR)
Description of bits 4 and 2 amended
481
13.2.4 Serial Control Register (SCR)
Description of bits 1 and 0 amended
483
Figure 13.2 Schematic Diagram of Smart Amended
Card Interface Pin Connections
484
Figure 13.3 Smart Card Interface Data Amended
Format
488, 489 Table 13.5 Examples of Bit Rate B (bit/s) Amended (ø = 20.00 MHz column added)
for Various BRR Settings (When n = 0)
Table 13.6 Examples of BRR Settings for
Bit Rate B (bit/s) (When n = 0)
491 to 493 13.3.6 Data Transfer Operations, Serial Amended
Data Transmission
497, 498 13.3.7 Operation in GSM Mode
Amended (Old section 13.3.7, Example of
Use in Software Standby Mode, replaced
with new section)
510
14.2.3 A/D Control Register (ADCR) Description of bits 7 and 6 amended
519 to 524 14.6 Usage Notes
(1) Amendment of setting range for analog
power supply pins etc.
(2) Deletion of module stop mode
interrupts
529
15.2.2 D/A Control Register (DACR)
Bit 5 description amended
532
15.4 Usage Notes
New