HD6432345 Datasheet, PDF (406/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

10.6.3 Contention between TCOR Write and Compare Match
During the T₂ state of a TCOR write cycle, the TCOR write has priority and the compare match
signal is disabled even if a compare match event occurs.
Figure 10.12 shows this operation.
ø
Address
TCOR write cycle by CPU
T₁
T₂
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
Compare match signal
TCOR write data
Disabled
Figure 10.12 Contention between TCOR Write and Compare Match
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