HD6432345 Datasheet, PDF (384/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Contention between Buffer Register Write and Input Capture: If the input capture signal is
generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the
write to the buffer register is not performed.
Figure 9.55 shows the timing in this case.
ø
Address
Write signal
Input capture
signal
TCNT
Buffer register write cycle
T1
T2
Buffer register
address
N
TGR
Buffer
register
M
N
M
Figure 9.55 Contention between Buffer Register Write and Input Capture
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