HD6432345 Datasheet, PDF (290/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Port G Data Direction Register (PGDDR)
Bit
:
7
6
5
4
3
2
1
0
—
—
— PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR
Modes 1, 4, 5*
Initial value : Undefined Undefined Undefined 1
0
0
0
0
R/W
:
—
—
—
W
W
W
W
W
Modes 2, 3, 6, 7*
Initial value : Undefined Undefined Undefined 0
0
0
0
0
R/W
:
—
—
—
W
W
W
W
W
PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an
undefined value will be read.
The PGDDR is initialized by a power-on reset and in hardware standby mode, to H'10 (bits 4 to 0)
in modes 1, 4, and 5*, and to H'00 (bits 4 to 0) in modes 2, 3, 6, and 7*. It retains its prior state
after a manual reset and in software standby mode. The OPE bit in SBYCR is used to select
whether the bus control output pins retain their output state or become high-impedance when a
transition is made to software standby mode.
• Modes 1 and 2*
Pin PG₄ functions as a bus control output pin (CS0) when the corresponding PGDDR bit is set
to 1, and as an input port when the bit is cleared to 0.
For pins PG₃ to PG₀, setting the corresponding PGDDR bit to 1 makes the pin an output port,
while clearing the bit to 0 makes the pin an input port.
• Modes 3 and 7*
Setting a PGDDR bit to 1 makes the corresponding port G pin an output port, while clearing
the bit to 0 makes the pin an input port.
• Modes 4, 5, and 6*
Pins PG₄ to PG₁ function as bus control output pins (CS0 to CS3) when the corresponding
PGDDR bits are set to 1, and as input ports when the bits are cleared to 0.
Note: * Modes 1 to 3 are not available on the F-ZTAT version.
Modes 2, 3, 6, and 7 are not available on the ROMless version.
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