HD6432345 Datasheet, PDF (416/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Bit 7—Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from
H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode.
Bit 7
WOVF
0
1
Description
[Clearing condition]
(Initial value)
Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF
[Setting condition]
Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer
operation
Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the
H8S/2345 Series if TCNT overflows during watchdog timer operation.
Bit 6
RSTE
Description
0
Reset signal is not generated if TCNT overflows*
(Initial value)
1
Reset signal is generated if TCNT overflows
Note: * The modules within the H8S/2345 Series are not reset, but TCNT and TCSR within the
WDT are reset.
Bit 5—Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows
during watchdog timer operation.
For details of the types of resets, see section 4, Exception Handling.
Bit 5
RSTS
0
1
Description
Power-on reset
Manual reset
(Initial value)
Bits 4 to 0—Reserved: Read-only bits, always read as 1.
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