HD6432345 Datasheet, PDF (366/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

TCLKA
TCLKB
Edge
detection
circuit
Channel 1
TCNT1
TGR1A
(speed period capture)
TGR1B
(position period capture)
TCNT0
+
TGR0A (speed control period)
–
TGR0C
+
(position control period)
–
TGR0B (pulse width capture)
TGR0D (buffer operation)
Channel 0
Figure 9.33 Phase Counting Mode Application Example
9.5 Interrupts
9.5.1 Interrupt Sources and Priorities
There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled
bit, allowing generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, but the priority order within
a channel is fixed. For details, see section 5, Interrupt Controller.
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