HD6432345 Datasheet, PDF (139/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Program execution status
No
Interrupt generated?
Yes
Yes
NMI
No
I=0
No
Yes
Hold pending
IRQ0
Yes
No
IRQ1
Yes
No
TEI1
Yes
Save PC and CCR
I←1
Read vector address
Branch to interrupt handling routine
Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in
Interrupt Control Mode 0
5.4.3 Interrupt Control Mode 2
Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts
by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR.
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