HD6432345 Datasheet, PDF (578/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Bit 3
FLSHE
0
1
Description
Flash control registers deselected in area H'FFFFC8 to H'FFFFCB
Flash control registers selected in area H'FFFFC8 to H'FFFFCB
(Initial value)
Bits 2 to 0—Reserved: Read-only bits, always read as 0.
17.7.5 RAM Emulation Register (RAMER)
Bit: 7
6
5
4
—
—
—
—
Initial value: 0
0
0
0
R/W: —
—
—
—
3
2
1
0
— RAMS RAM1 RAM0
0
0
0
0
—
R/W R/W R/W
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER is initialized to H'00 by a reset and in hardware
standby mode. It is not initialized in software standby mode. RAMER settings should be made in
user mode or user program mode.
Flash memory area divisions are shown in table 17.13. To ensure correct operation of the
emulation function, the ROM for which RAM emulation is performed should not be accessed
immediately after this register has been modified. Normal execution of an access immediately
after register modification is not guaranteed.
Bits 7 to 3—Reserved: These bits are always read as 0.
Bit 2—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in
RAM. When RAMS = 1, all flash memory block are program/erase-protected.
Bit 2
RAMS
0
1
Description
Emulation not selected
Program/erase-protection of all flash memory blocks is disabled
Emulation selected
Program/erase-protection of all flash memory blocks is enabled
(Initial value)
Bits 1 and 0—Flash Memory Area Selection (RAM1, RAM0): These bits are used together
with bit 2 to select the flash memory area to be overlapped with RAM. (See table 17.13.)
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