HD6432345 Datasheet, PDF (154/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

6.2.2 Access State Control Register (ASTCR)
Bit
:
Initial value :
R/W
:
7
AST7
1
R/W
6
AST6
1
R/W
5
AST5
1
R/W
4
AST4
1
R/W
3
AST3
1
R/W
2
AST2
1
R/W
1
AST1
1
R/W
0
AST0
1
R/W
ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access
space or a 3-state access space.
ASTCR sets the number of access states for the external memory space. The number of access
states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR.
In normal mode*, the settings of bits AST7 to AST1 have no effect on operation.
ASTCR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is to be designated as a 2-state access space or a 3-state access space. In
normal mode*, only part of area 0 is enabled, and the AST0 bit selects whether external space is
to be designated for 2-state access or 3-state access.
Wait state insertion is enabled or disabled at the same time.
Note: * ZTAT, mask ROM, and ROMless versions only.
Bit n
ASTn
0
1
Description
Area n is designated for 2-state access
Wait state insertion in area n external space is disabled
Area n is designated for 3-state access
Wait state insertion in area n external space is enabled
(Initial value)
(n = 7 to 0)
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