HD6432345 Datasheet, PDF (422/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

ø
TCNT
Overflow signal
(internal signal)
H'FF
H'00
OVF
Figure 11.6 Timing of Setting of OVF
11.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time,
the WDTOVF signal* goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an
internal reset signal is generated for the entire H8S/2345 Series chip. Figure 11.7 shows the timing
in this case.
Note: * The WDTOVF pin function is not supported by the F-ZTAT version.
ø
TCNT
H'FF
H'00
Overflow signal
(internal signal)
WOVF
WDTOVF signal*
132 states
Internal reset
signal
518 states
Note: * The WDTOVF pin function is not supported by the F-ZTAT version.
Figure 11.7 Timing of Setting of WOVF
407