HD6432345 Datasheet, PDF (412/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

11.1.3 Pin Configuration
Table 11.1 describes the WDT output pin.
Table 11.1 WDT Pin
Name
Symbol I/O
Function
Watchdog timer overflow
WDTOVF* Output Outputs counter overflow signal in watchdog
timer mode
Note: * The WDTOVF pin function is not supported by the F-ZTAT version.
11.1.4 Register Configuration
The WDT has three registers, as summarized in table 11.2. These registers control clock selection,
WDT mode switching, and the reset signal.
Table 11.2 WDT Registers
Address*¹
Name
Abbreviation R/W
Initial Value Write*² Read
Timer control/status register TCSR
R/(W)*³ H'18
H'FFBC H'FFBC
Timer counter
TCNT
R/W H'00
H'FFBC H'FFBD
Reset control/status register RSTCSR
R/(W)*³ H'1F
H'FFBE H'FFBF
Notes: 1. Lower 16 bits of the address.
2. For details of write operations, see section 11.2.4, Notes on Register Access.
3. Only a write of 0 is permitted to bit 7, to clear the flag.
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