HD6432345 Datasheet, PDF (717/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table A.2 Instruction Codes (cont)
Instruc-
tion
Mnemonic
Size
LDC
LDM
LDMAC
MAC
MOV
LDC @aa:32,CCR
W
LDC @aa:32,EXR
W
LDM.L @SP+, (ERn-ERn+1) L
LDM.L @SP+, (ERn-ERn+2) L
LDM.L @SP+, (ERn-ERn+3) L
LDMAC ERs,MACH
L
LDMAC ERs,MACL
L
MAC @ERn+,@ERm+ —
MOV.B #xx:8,Rd
B
MOV.B Rs,Rd
B
MOV.B @ERs,Rd
B
MOV.B @(d:16,ERs),Rd B
MOV.B @(d:32,ERs),Rd B
MOV.B @ERs+,Rd
B
MOV.B @aa:8,Rd
B
MOV.B @aa:16,Rd
B
MOV.B @aa:32,Rd
B
MOV.B Rs,@ERd
B
MOV.B Rs,@(d:16,ERd) B
MOV.B Rs,@(d:32,ERd) B
MOV.B Rs,@-ERd
B
MOV.B Rs,@aa:8
B
MOV.B Rs,@aa :16
B
MOV.B Rs,@aa:32
B
MOV.W #xx:16,Rd
W
MOV.W Rs,Rd
W
MOV.W @ERs,Rd
W
MOV.W @(d:16,ERs),Rd W
MOV.W @(d:32,ERs),Rd W
1st byte 2nd byte 3rd byte 4th byte
01406B20
0
1
4
1
6
B
20
0
1
1
0
6D
7 0 ern+1
0
1
2
0
6D
7 0 ern+2
0
1
3
0
6D
7 0 ern+3
Cannot be used in the H8S/2345 Series
Instruction Format
5th byte 6th byte 7th byte
abs
abs
F rd
IMM
0 C rs rd
6 8 0 ers rd
6 E 0 ers rd
disp
7
8 0 ers 0
6
A
2 rd
disp
6 C 0 ers rd
2 rd
abs
6 A 0 rd
abs
6 A 2 rd
abs
6 8 1 erd rs
6 E 1 erd rs
disp
7 8 0 erd 0 6 A A rs
disp
6 C 1 erd rs
3 rs
abs
6 A 8 rs
abs
6 A A rs
abs
7 9 0 rd
IMM
0 D rs rd
6 9 0 ers rd
6 F 0 ers rd
disp
7 8 0 ers 0 6 B 2 rd
disp
8th byte
9th byte 10th byte