HD6432345 Datasheet, PDF (630/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Bit 6 Bit 5 Bit 4
STS2 STS1 STS0 Description
0
0
0
Standby time = 8192 states
1
Standby time = 16384 states
1
0
Standby time = 32768 states
1
Standby time = 65536 states
1
0
0
Standby time = 131072 states
1
Standby time = 262144 states
1
0
Reserved
1
Standby time = 16 states*
Note: * Not used on the F-ZTAT version.
(Initial value)
Bit 3—Output Port Enable (OPE): Specifies whether the output of the address bus and bus
control signals (CS0 to CS3, AS, RD, HWR, LWR) is retained or set to the high-impedance state
in software standby mode.
Bit 3
OPE
0
1
Description
In software standby mode, address bus and bus control signals are high-impedance
In software standby mode, address bus and bus control signals retain output state
(Initial value)
Bits 2 and 1—Reserved: Read-only bits, always read as 0.
Bit 0—Reserved: This bit can be read or written to, but only 0 should be written.
19.2.2 System Clock Control Register (SCKCR)
Bit
:
7
6
5
4
PSTOP —
—
—
Initial value :
0
0
0
0
R/W
: R/W
R/W
—
—
3
2
1
0
—
SCK2 SCK1 SCK0
0
0
0
0
—
R/W R/W R/W
SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-
speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
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