HD6432345 Datasheet, PDF (787/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

TIOR5—Timer I/O Control Register 5
H'FEA2
TPU5
Bit
:
Initial value :
Read/Write :
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
TGR5A I/O Control
0 0 0 0 TGR5A Output disabled
1
is output
compare
Initial output is 0
0 output at compare match
1 0 ^{register output}
1 output at compare match
1
Toggle output at compare match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare match
1 * 0 0 _{TGR5A Capture input}
Input capture at rising edge
1
is input
capture
source is TIOCA5
pin
Input capture at falling edge
1 * ^register
Input capture at both edges
* : Don’t care
TGR5B I/O Control
0 0 0 0 TGR5B Output disabled
is output
1 _compare Initial output is 0
1 0 ^{register output}
0 output at compare match
1 output at compare match
1
Toggle output at compare match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare match
1 * 0 0 TGR5B Capture input
Input capture at rising edge
is input source is TIOCB5
1 _{capture pin}
Input capture at falling edge
1 * ^register
Input capture at both edges
* : Don’t care
778