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HD6432345 Datasheet, PDF (447/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual | |||
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The BRR setting is found from the following formulas.
Asynchronous mode:
Ï
N=
64 Ã 22nâ1 Ã B
à 106 â 1
Clocked synchronous mode:
Ï
N=
à 106 â 1
8 Ã 22nâ1 Ã B
Where B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ⤠N ⤠255)
ø: Operating frequency (MHz)
n: Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
SMR Setting
n
Clock
CKS1
CKS0
0
ø
0
0
1
ø/4
0
1
2
ø/16
1
0
3
ø/64
1
1
The bit rate error in asynchronous mode is found from the following formula:
Error (%) =
Ï Ã 106
(N + 1) Ã B Ã 64 Ã 22nâ1 â 1 Ã 100
433
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