HD6432345 Datasheet, PDF (798/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

BCRH—Bus Control Register H
H'FED4
Bus Controller
Bit
:
7
6
5
4
3
2
1
0
ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 —
—
—
Initial value :
1
1
0
1
0
0
0
0
Read/Write : R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
Only 0 should be written
to these bits
Burst Cycle Select 0
0 Max. 4 words in burst access
1 Max. 8 words in burst access
Burst Cycle Select 1
0 Burst cycle comprises 1 state
1 Burst cycle comprises 2 states
Area 0 Burst ROM Enable
0 Area 0 is basic bus interface
1 Area 0 is burst ROM interface
Idle Cycle Insert 0
0 Idle cycle not inserted in case of successive external read
and external write cycles
1 Idle cycle inserted in case of successive external read
and external write cycles
Idle Cycle Insert 1
0 Idle cycle not inserted in case of successive external
read cycles in different areas
1 Idle cycle inserted in case of successive external
read cycles in different areas
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