HD6432345 Datasheet, PDF (212/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

7.3.8 Chain Transfer
Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 7.9 shows the memory map for chain transfer.
Source
DTC vector
address
Register information
start address
Register information
CHNE = 1
Register information
CHNE = 0
Destination
Source
Destination
Figure 7.9 Chain Transfer Memory Map
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
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