HD6432345 Datasheet, PDF (900/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table D.1 I/O Port States in Each Processing State (cont)
Port Name
Pin Name
PF₇/ø
PF₆/AS
PF₅/RD
PF₄/HWR
PF₃/LWR/
IRQ3
PF₂/WAIT/
IRQ2
PF₁/BACK/
IRQ1
PF₀/BREQ/
IRQ0
PG₄/CS0
MCU
Operating
Mode
1, 2, 4 to 6
3, 7
1, 2, 4 to 6
3, 7
1, 2, 4 to 6
3, 7
1, 2, 4 to 6
3, 7
1, 2, 4 to 6
3, 7
1, 4, 5
2, 6
3, 7
Power-
On
Manual
Reset Reset
Hardware Software
Standby Standby
Mode
Mode
Bus
Release
State
Program
Execution
State
Sleep Mode
Clock [DDR = 0] T
output T
[DDR = 1]
Clock
output
[DDR = 0]
Input port
[DDR = 1]
H
[DDR = 0]
Input port
[DDR = 1]
Clock
output
[DDR = 0]
Input port
[DDR = 1]
Clock
output
T
kept
T
[DDR = 0]
Input port
[DDR = 1]
H
[DDR = 0]
Input port
[DDR = 1]
Clock
output
[DDR = 0]
Input port
[DDR = 1]
Clock
output
H
H*
T
[OPE = 0]
T
T
[OPE = 1]
H
AS, RD,
HWR, LWR
T
kept
T
kept
kept
I/O port
T
[WAITE = 0] T
kept
[WAITE = 1]
T
[WAITE = 0]
kept
[WAITE = 1]
T
[WAITE = 0] [WAITE = 0]
kept
I/O port
[WAITE = 1] [WAITE = 1]
T
WAIT
T
kept
T
kept
kept
I/O port
T
[BRLE = 0] T
kept
[BRLE = 1]
BACK
[BRLE = 0]
L
kept
[BRLE = 1]
H
[BRLE = 0]
I/O port
[BRLE = 1]
BACK
T
kept
T
kept
kept
I/O port
T
[BRLE = 0] T
kept
[BRLE = 1]
BREQ
[BRLE = 0]
T
kept
[BRLE = 1]
T
[BRLE = 0]
I/O port
[BRLE = 1]
BREQ
T
kept
T
kept
kept
I/O port
H
[DDR = 0] T
T
T
[DDR = 1]
H*
[DDR · OPE = 0] T
T
[DDR · OPE = 1]
H
[DDR = 0]
Input port
[DDR = 1]
CS0
T
kept
T
kept
kept
I/O port
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