HD6432345 Datasheet, PDF (531/907 Pages) Hitachi Semiconductor – H8S/2345 F-ZTAT Hardware Manual

Table 14.4 A/D Conversion Time (Single Mode)
Item
Symbol
Min
A/D conversion start delay
t_D
10
Input sampling time
t _SPL
—
A/D conversion time
t _CONV
259
Note: Values in the table are the number of states.
CKS = 0
Typ Max
— 17
63 —
— 266
CKS = 1
Min Typ Max
6
—9
— 31 —
131 — 134
14.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as if the ADST bit has been set to 1 by software. Figure 14.6 shows the
timing.
ø
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 14.6 External Trigger Input Timing
518