SH7203 Datasheet, PDF (991/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Controller Area Network (RCAN-TL1)
• RXPR0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RXPR0[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * Only when writing a ‘1’ to clear.
Bit 15 to 0 — Configurable receive mailbox locations corresponding to each mailbox position
from 15 to 0 respectively.
Bit[15:0]: RXPR0
0
1
Description
[Clearing Condition] Writing ‘1’ (Initial value)
Corresponding Mailbox received a CAN Data Frame
[Setting Condition]
Completion of Data Frame receive on corresponding mailbox
Rev. 2.00 Apr. 16, 2008 Page 961 of 1652
REJ09B0313-0200