SH7203 Datasheet, PDF (1438/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 28 Power-Down Modes
28.2.10 Deep Standby Control Register (DSCTR)
DSCTR is an 8-bit readable/writable register that selects whether to retain the contents of the
corresponding area of the on-chip RAM (for data retention) in deep standby mode. Only byte
access is valid.
When the RRAMKP3 to 0 bits are set to 1, the contents of the corresponding area of the on-chip
RAM (for data retention) are retained in deep standby mode. When these bits are cleared to 0, the
contents of the corresponding area of the on-chip RAM (for data retention) are not retained in
deep standby mode.
Note: When writing to this register, see section 28.4, Usage Notes.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
RRAM RRAM RRAM RRAM
KP3 KP2 KP1 KP0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R R/W R/W R/W R/W
Bit
7 to 4
3
2
Initial
Bit Name Value R/W Description
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
RRAMKP3 0
R/W On-Chip RAM Storage Area 3 (corresponding area of
on-chip RAM (for data retention): page 3*)
0: The contents of the corresponding on-chip RAM
(for data retention) area are not retained in deep
standby mode.
1: The contents of the corresponding on-chip RAM
(for data retention) area are retained in deep
standby mode.
RRAMKP2 0
R/W On-Chip RAM Storage Area 2 (corresponding area of
on-chip RAM (for data retention): page 2*)
0: The contents of the corresponding on-chip RAM
(for data retention) area are not retained in deep
standby mode.
1: The contents of the corresponding on-chip RAM
(for data retention) area are retained in deep
standby mode.
Rev. 2.00 Apr. 16, 2008 Page 1408 of 1652
REJ09B0313-0200