SH7203 Datasheet, PDF (163/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Exception Handling
5.6 Exceptions Triggered by Instructions
5.6.1 Types of Exceptions Triggered by Instructions
Exception handling can be triggered by trap instructions, slot illegal instructions, general illegal
instructions, integer division exceptions, and FPU exceptions, as shown in table 5.10.
Table 5.10 Types of Exceptions Triggered by Instructions
Type
Trap instruction
Slot illegal
instructions
General illegal
instructions
Integer division
exceptions
Source Instruction
Comment
TRAPA
Undefined code placed
immediately after a delayed
branch instruction (delay slot)
(including FPU instructions and
FPU-related CPU instructions in
FPU module standby state),
instructions that rewrite the PC,
32-bit instructions, RESBANK
instruction, DIVS instruction, and
DIVU instruction
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF, JSR/N, RTV/N
32-bit instructions: BAND.B, BANDNOT.B,
BCLR.B, BLD.B, BLDNOT.B, BOR.B,
BORNOT.B, BSET.B, BST.B, BXOR.B,
MOV.B@disp12, MOV.W@disp12,
MOV.L@disp12, MOVI20, MOVI20S,
MOVU.B, MOVU.W.
Undefined code anywhere
besides in a delay slot (including
FPU instructions and FPU-related
CPU instructions in FPU module
standby statute)
Division by zero
DIVU, DIVS
Negative maximum value ÷ (−1) DIVS
FPU exceptions
Starts when detecting invalid
FADD, FSUB, FMUL, FDIV, FMAC,
operation exception defined by FCMP/EQ, FCMP/GT, FLOAT, FTRC,
IEEE754, division-by-zero
FCNVDS, FCNVSD, FSQRT
exception, overflow, underflow, or
inexact exception.
Rev. 2.00 Apr. 16, 2008 Page 133 of 1652
REJ09B0313-0200