SH7203 Datasheet, PDF (927/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

(1) Transmission Using DMA Controller
Section 18 Serial Sound Interface (SSI)
Start
Release from reset,
set SSICR configuration bits.
Set up DMA controller to
provide transmission data as
required.
Enable SSI module,
enable DMA,
enable error interrupts.
Wait for interrupt from DMAC or SSI.
Define TRMD, EN, SCKD, SWSD,
MUEN, DEL, PDTA, SDTA, SPDP,
SWSP, SCKP, SWL, DWL, CHNL
EN = 1,
DMEN = 1,
UIEN = 1, OIEN = 1
Yes
SSI error interrupt?
No
No
DMAC:
End of Tx data?
Yes
Yes
More data to be send?
No
Disable SSI module,
disable DMA,
disable error interrupts,
enable Idle interrupt.
EN = 0,
DMEN = 0
UIEN = 0, OIEN = 0,
IIEN = 1
Wait for idle interrupt
from SSI module.
End*
Note: * If the SSI encounters an error interrupt underflow/overflow,
go back to the start in the flowchart again.
Figure 18.20 Transmission Using DMA Controller
Rev. 2.00 Apr. 16, 2008 Page 897 of 1652
REJ09B0313-0200