SH7203 Datasheet, PDF (172/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Interrupt Controller (INTC)
Figure 6.1 shows a block diagram of the INTC.
IRQOUT
NMI
IRQ7 to IRQ0
PINT7 to PINT0
UBC
H-UDI
DMAC
USB
LCDC
CMT
BSC
WDT
MTU2
ADC
IIC3
SCIF
SSU
SSI
FLCTL
RTC
RCAN-TL1
Input control
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
ICR0
ICR2
PINTER
IBCR
ICR1
IRQRR
PIRR
IBNR
Com-
parator
Priority
identifier
Interrupt
request
SR
I3 I2 I1 I0
CPU
IPR
IPR01, IPR02,
IPR05 to IPR17
[Legend]
UBC:
H-UDI:
DMAC:
USB:
LCDC:
CMT:
BSC:
WDT:
MTU2:
ADC:
IIC3:
SCIF:
SSU:
SSI:
Module bus
INTC
Bus
interface
User break controller
User debugging interface
Direct memory access controller
USB2.0 host/function module
LCDC controller
Compare match timer
Bus state controller
Watchdog timer
Multi-function timer pulse unit 2
A/D converter
I²C bus interface 3
Serial communication interface with FIFO
Synchronous serial communication unit
Serial sound interface
FLCTL:
AND/NAND flash memory controller
RTC:
Realtime clock
RCAN-TL1:
Controller area network
ICR0:
Interrupt control register 0
ICR1:
Interrupt control register 1
ICR2:
Interrupt control register 2
IRQRR:
IRQ interrupt request register
PINTER:
PINT interrupt enable register
PIRR:
PINT interrupt request register
IBCR:
Bank control register
IBNR:
Bank number register
IPR01, IPR02, IPR05 to IPR17: Interrupt priority registers 01, 02,
05 to 17
Figure 6.1 Block Diagram of INTC
Rev. 2.00 Apr. 16, 2008 Page 142 of 1652
REJ09B0313-0200