SH7203 Datasheet, PDF (1129/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
23.3.3 Device State Control Register (DVSTCTR)
DVSTCTR is a register that controls and confirms the state of the USB data bus.
This register is initialized by a power-on reset. After a software reset, WKUP is undefined but bits
other than WKUP are initialized. After a USB bus reset, WKUP is initialized but RESUME is
undefined.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
UAC
KEY0
-
-
UAC
KEY1
-
-
- WKUP RWUPE USBRSTRESUME UACT -
-
RHST[1:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R
R R/W R
R
R R/W R/W R/W R/W R/W R
R
R
R
Bit
Bit Name
15
UACKEY0
14, 13 ⎯
12
UACKEY1
11 to 9 ⎯
Initial
Value R/W Description
0
R/W USBAC Key 0
Writing to the HOSTPCC bit in the test register is not
possible unless this bit is set. For details, see section
23.5.2, Procedure for Setting the USB Transceiver.
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
R/W USBAC Key 1
Writing to the HOSTPCC bit in the test register is not
possible unless this bit is set. For details, see section
23.5.2, Procedure for Setting the USB Transceiver.
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Apr. 16, 2008 Page 1099 of 1652
REJ09B0313-0200