SH7203 Datasheet, PDF (140/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 4 Clock Pulse Generator (CPG)
Initial
Bit
Bit Name Value R/W Description
14
CKOEN2 0
R/W Clock Output Enable 2
Specifies whether the CKIO pin outputs clock signals
or the CKIO pin is fixed low when the frequency-
multiplier of the PLL circuit is changed.
If this bit is set to 1, the CKIO pin is fixed low while the
frequency-multiplier of the PLL circuit is changed.
Therefore, the malfunction of an external circuit
caused by an unstable CKIO clock when the
frequency-multiplier of the PLL circuit is changed can
be prevented. In clock operating mode 2, the CKIO
pin functions as an input regardless of the value of
this bit.
0: Outputs clock
1: Outputs low level
13, 12 CKOEN[1:0] 00
R/W Clock Output Enable
Specifies the CKIO pin outputs clock signals, or is set
to a fixed level or high impedance (Hi-Z) during
normal operation mode, release of bus mastership,
standby mode, or cancellation of standby mode.
If these bits are set to 01, the CKIO pin is fixed at low
during standby mode or cancellation of standby
mode. Therefore, the malfunction of an external circuit
caused by an unstable CKIO clock during cancellation
of standby mode can be prevented. In clock operating
mode 2, the CKIO pin functions as an input
regardless of the value of these bits. In deep standby
mode, the normal state is retained.
In normal In release of bus In standby
operation mastership
mode
00 Output
Output off
(Hi-Z)
Output off
(Hi-Z)
01 Output Output
Low-level
output
10 Output Output
Output
(unstable clock
output)
11 Output off Output off
(Hi-Z)
(Hi-Z)
Output off
(Hi-Z)
Rev. 2.00 Apr. 16, 2008 Page 110 of 1652
REJ09B0313-0200