SH7203 Datasheet, PDF (167/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Exception Handling
5.7 When Exception Sources Are Not Accepted
When an address error, FPU exception, register bank error (overflow), or interrupt is generated
immediately after a delayed branch instruction, it is sometimes not accepted immediately but
stored instead, as shown in table 5.11. When this happens, it will be accepted when an instruction
that can accept the exception is decoded.
Table 5.11 Exception Source Generation Immediately after Delayed Branch Instruction
Exception Source
Point of Occurrence
Address
Error
FPU
Exception
Register Bank
Error (Overflow) Interrupt
Immediately after a delayed Not accepted Not accepted Not accepted
branch instruction^*
Not accepted
Note: * Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Rev. 2.00 Apr. 16, 2008 Page 137 of 1652
REJ09B0313-0200