SH7203 Datasheet, PDF (1082/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 22 AND/NAND Flash Memory Controller (FLCTL)
Bit
17
16
15
14
13, 12
Initial
Bit Name Value
QTSEL 0
—
0
FCKSEL 0
—
0
ECCPOS 00
[1:0]
R/W
R/W
R
R/W
R
R/W
Description
Select Dividing Rates for Flash Clock
Selects the dividing rate of clock FCLK in the flash
memory. This bit is used together with FCKSEL.
• QTSEL = 0, FCKSEL = 0: Divides a clock (Pφ)
provided from the CPG by two and uses it as FCLK.
• QTSEL = 0, FCKSEL = 1: Uses a clock (Pφ)
provided from the CPG as FCLK.
• QTSEL = 1, FCKSEL = 0: Divides a clock (Pφ)
provided from the CPG by four and uses it as FCLK.
• QTSEL = 1, FCKSEL = 1: Setting prohibited
Reserved
This bit is always read as 0. The write value should
always be 0.
Flash Clock Select
Selects the dividing rate of clock FCLK in the flash
memory. This bit is used together with QTSEL. Refer to
the description of QTSEL.
Reserved
This bit is always read as 0. The write value should
always be 0.
ECC Position Specification 1 and 0
Specify the position (0/4th/8th byte) to place the ECC in
the control code area.
00: Places the ECC at the 0 to 7th byte of control code
area
01: Places the ECC at the 4th to 11th byte of control
code area
10: Places the ECC at the 8th to 15th byte of control
code area
11: Setting prohibited
Rev. 2.00 Apr. 16, 2008 Page 1052 of 1652
REJ09B0313-0200