SH7203 Datasheet, PDF (907/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 18 Serial Sound Interface (SSI)
Bit
6 to 4
Bit Name
CKDV[2:0]
Initial
Value
000
3
MUEN
0
2
⎯
0
1
TRMD
0
0
EN
0
R/W
R/W
R/W
R
R/W
R/W
Description
Serial Oversampling Clock Division Ratio
Sets the ratio between oversampling clock* and the
serial bit clock. When the SCKD bit is 0, the setting of
these bits is ignored. The serial bit clock is used in the
shift register and is supplied from the SSISCK pin.
000: Serial bit clock frequency = Oversampling clock Frequency/1
001: Serial bit clock frequency = Oversampling clock frequency/2
010: Serial bit clock frequency = Oversampling clock frequency/4
011: Serial bit clock frequency = Oversampling clock frequency/8
100: Serial bit clock frequency = Oversampling clock frequency/16
101: Serial bit clock frequency = Oversampling clock frequency/6
110: Serial bit clock frequency = Oversampling clock frequency/12
111: Setting prohibited
Note: * Oversampling clock is selected by the setting
of the SCSR bits in the PFC. For details, see
section 25, Pin Function Controller (PFC).
Mute Enable
0: Module is not muted.
1: Module is muted.
Reserved
The read value is undefined. The write value should
always be 0.
Transmit/Receive Mode Select
0: Module is in receive mode.
1: Module is in transmit mode.
SSI Module Enable
0: Module is disabled.
1: Module is enabled.
Rev. 2.00 Apr. 16, 2008 Page 877 of 1652
REJ09B0313-0200