SH7203 Datasheet, PDF (26/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

24.4.1 LCD Module Sizes which can be Displayed in this LCDC ................................ 1261
24.4.2 Limits on the Resolution of Rotated Displays, Burst Length,
and Connected Memory (SDRAM) .................................................................... 1262
24.4.3 Color Palette Specification ................................................................................. 1269
24.4.4 Data Format ........................................................................................................ 1270
24.4.5 Setting the Display Resolution............................................................................ 1273
24.4.6 Power Management Registers............................................................................. 1273
24.4.7 Operation for Hardware Rotation ....................................................................... 1278
24.5 Clock and LCD Data Signal Examples............................................................................ 1281
24.6 Usage Notes ..................................................................................................................... 1291
24.6.1 Procedure for Halting Access to Display Data Storage VRAM
(Synchronous DRAM in Area 3) ........................................................................ 1291
Section 25 Pin Function Controller (PFC) ......................................................1293
25.1 Features............................................................................................................................ 1299
25.2 Register Descriptions ....................................................................................................... 1300
25.2.1 Port B I/O Register L (PBIORL) ........................................................................ 1301
25.2.2 Port B Control Registers L1 to L4 (PBCRL1 to PBCRL4) ................................ 1302
25.2.3 Port C I/O Register L (PCIORL) ........................................................................ 1307
25.2.4 Port C Control Register L1 to L4 (PCCRL1 to PCCRL4) .................................. 1307
25.2.5 Port D I/O Register L (PDIORL)........................................................................ 1313
25.2.6 Port D Control Registers L1 to L4 (PDCRL1 to PDCRL4)................................ 1313
25.2.7 Port E I/O Register L (PEIORL)......................................................................... 1330
25.2.8 Port E Control Registers L1 to L4 (PECRL1 to PECRL4) ................................. 1330
25.2.9 Port F I/O Registers H, L (PFIORH, PFIORL)................................................... 1337
25.2.10 Port F Control Registers H1 to H4, L1 to L4
(PFCRH1 to PFCRH4, PFCRL1 to PFCRL4) .................................................... 1338
25.2.11 IRQOUT Function Control Register (IFCR) ...................................................... 1352
25.2.12 SSI Oversampling Clock Selection Register (SCSR) ......................................... 1353
25.3 Switching Pin Function of Port A .................................................................................... 1355
25.4 Usage Notes ..................................................................................................................... 1356
Section 26 I/O Ports.........................................................................................1357
26.1 Features............................................................................................................................ 1357
26.2 Port A............................................................................................................................... 1358
26.2.1 Register Descriptions.......................................................................................... 1358
26.2.2 Port A Data Register L (PADRL) ....................................................................... 1358
26.3 Port B ............................................................................................................................... 1360
26.3.1 Register Descriptions.......................................................................................... 1360
26.3.2 Port B Data Register L (PBDRL) ....................................................................... 1361
Rev. 2.00 Apr. 16, 2008 Page xxvi of xxx
REJ09B0313-0200