SH7203 Datasheet, PDF (1188/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
11 to 3 ⎯
2 to 0 IITV
Initial
Value R/W
All 0 R
000 R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Interval Error Detection Interval
These bits specify the interval timing in terms of the
frame timing divided by an n-th power of 2.
These bits are valid only when the function controller
function and isochronous transfer are selected. In
other words, these bits can be set when PIPE1 and
PIPE2 are selected.
• OUT-direction: When this module does not
receive the OUT token from the host until the
time indicated by these bits, it detects an interval
error on the NRDY interrupt and generates the
NRDY interrupt.
• IN-direction: When this module does not receive
the IN token from the host until the time indicated
by these bits, it flushes (clears) the buffer if IFIS
= 1.
When the host controller function is selected, these
bits are valid for isochronous transfers and interrupt
transfers.
Rev. 2.00 Apr. 16, 2008 Page 1158 of 1652
REJ09B0313-0200