SH7203 Datasheet, PDF (1433/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 28 Power-Down Modes
28.2.7 System Control Register 1 (SYSCR1)
SYSCR1 is an 8-bit readable/writable register that enables or disables access to the on-chip RAM
(high-speed). Only byte access is valid.
When an RAME bit is set to 1, the corresponding on-chip RAM (high-speed) area is enabled.
When an RAME bit is cleared to 0, the corresponding on-chip RAM (high-speed) area cannot be
accessed. In this case, an undefined value is returned when reading data or fetching an instruction
from the on-chip RAM (high-speed), and writing to the on-chip RAM (high-speed) is ignored. The
initial value of an RAME bit is 1.
Note that when clearing the RAME bit to 0 to disable the on-chip RAM (high-speed), be sure to
execute an instruction to read from or write to the same arbitrary address in each page before
setting the RAME bit. If such an instruction is not executed, the data last written to each page may
not be written to the on-chip RAM (high-speed). Furthermore, an instruction to access the on-chip
RAM (high-speed) should not be located immediately after the instruction to write to SYSCR1. If
an on-chip RAM (high-speed) access instruction is set, normal access is not guaranteed.
When setting the RAME bit to 1 to enable the on-chip RAM (high-speed), an instruction to read
SYSCR1 should be located immediately after the instruction to write to SYSCR1. If an instruction
to access the on-chip RAM (high-speed) is located immediately after the instruction to write to
SYSCR1, normal access is not guaranteed.
Note: When writing to this register, see section 28.4, Usage Notes.
Bit: 7
6
5
4
3
2
1
0
-
-
-
- RAME3 RAME2 RAME1 RAME0
Initial value: 1
1
1
1
1
1
1
1
R/W: R R R R R/W R/W R/W R/W
Rev. 2.00 Apr. 16, 2008 Page 1403 of 1652
REJ09B0313-0200