SH7203 Datasheet, PDF (689/1686 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Compare Match Timer (CMT)
Initial
Bit
Bit Name Value R/W Description
1, 0
CKS[1:0] 00
R/W Clock Select
These bits select the clock to be input to CMCNT from
four internal clocks obtained by dividing the peripheral
clock (Pφ). When the STR bit in CMSTR is set to 1,
CMCNT starts counting on the clock selected with bits
CKS[1:0].
00: Pφ/8
01: Pφ/32
10: Pφ/128
11: Pφ/512
Note: * Only 0 can be written to clear the flag after 1 is read.
Rev. 2.00 Apr. 16, 2008 Page 659 of 1652
REJ09B0313-0200